The present invention relates to a system and method for creating electronic circuit designs and in particular to a system and method for programmatically adding and manipulating logic elements surrounding terminals to create new designs or modify existing designs of electronic circuits.
In recent years, use of software tools to design electronic circuits has increased dramatically. Prior to designing an ASIC (Application Specific Integrated Circuit) or a programmable FPGA (Field Programmable Gate Array) it is necessary to add specific pads, ports and possibly logic at tristate outputs to terminals of each design.
Referring to FIG. 1 an electronic circuit 10 is shown, which circuit is either a fixed ASIC or a programmable FPGA design. The circuit has a finite size, with a portion of the surface area of the circuit being dedicated to internal circuits 12 which perform the functions of the chip. The remainder of the chip is dedicated to pads 14 or ports 16.
As shown in FIG. 1 on an FPGA chip, there is an inner rectangular array of logic 13, surrounded by an outer (rectangular) ring of logic 15. Each identical element 14 of the outer ring of logic is referred to as a "pad". These pads are used for a number of standard functions including but not limited to controlling outside loads, buffering and providing surge protection. When a "device" is mounted into a "package" some, but perhaps not all, of the "pads" are connected to the physical package pins or "ports" 16. When a designer captures a schematic, he places symbols for "pad" logic, and also indicates which of the "pad" cells must be connected to physical package pins. This indication is made by attaching "port" symbols to most or all of the "pad" symbols.
With most chip designs, the chip designer desires to maximize the circuitry on the chip to perform as many functions for the chip as possible. Because the chips have a fixed size, the number of internal circuits 12 is limited by the dimensions of the available chip surface assigned to the internal circuits 12. In many cases, however, while the circuit 10 contains the maximum internal circuitry 12, the pads 14 and ports 16 often contain unused circuitry or are entirely unused when automatic circuit generating tools are used. FIG. 2 shows a circuit design 19 before pads and ports are added and FIG. 3 shows a circuit design in which input ports 20, input pads 22, output pads 24 and output ports 26 have been added automatically without any logic being mapped to the pads.
The particular pads and ports in any circuit depend on the particular circuit technology (i.e., family of chips) being used. All of these pads and ports are utilized to interface either with other circuits or with other parts of the system in which the circuit is a component. These pads and ports enable technology-specific back end placement and routing tools to function. The added ports indicate the direction of signal flow through the terminals. The added pads corresponding to physical pads on the target chip and indicate signal flow direction. Pads may also contain logic in addition to the logic needed to perform the standard pad functions described above. If such extra logic available within such pads can be utilized, the resources on the chip will be capable of performing more functions which may result in fewer overall devices on the board.
Another goal of any circuit design is to minimize the number of pads and ports that are utilized so that more functions that require pads and ports can be provided on the device. In the case where tristate outputs are wired together, existing automatic design tools add one pad and one port for each tristate output in the circuit which often results in the utilization of a significant number of available pads and ports on the device. If the number of pads and ports required to be assigned to tristate outputs can be reduced, the device will be able to perform additional functions.
In the past, pads and ports were provided either explicitly by the designer or inefficiently added in an unconfigurable manner which failed to fully utilize available chip resources. This was a tedious process and was only possible because the designer was familiar with the design that was being presented to back end tools. Now that circuit design tools enable complex structural designs to be explicitly created and since such complex structural designs may also be created through synthesis from high level behavioral languages like VHDL, it is much more difficult for a designer to add the appropriate pads and ports and reduce the number of pads and ports required for tristate outputs because the circuit may be designed on a high-level conceptual basis.
To make this process easier, designers will often use a tool commonly called a "partitioner" which breaks an original chip design into subdesigns each of which observe the characteristics of the target technology which will sometimes be used for prototyping. Because the design output is now generally software derived, the manual addition of pads and ports and attempts to minimize pads and ports is even more tedious and more difficult as the designer is often unfamiliar with the specific characteristics and available resources on each targeted chip. To date, there are no systems which will automatically add configurable pads and ports in an optimized manner and reduce pads and ports required for tristate outputs wired together. Further complicating this problem is that it is difficult to ensure that net names at terminals are preserved, especially in the case of bidirectional terminals. This is important because terminals are recognized in devices by their net name.
It is therefore a principal object of the present invention to provide a system and method for programmatically adding and manipulating logic at terminals of electronic circuits.
It is the further object of the present invention to provide a system and method for automatically adding pads and ports to generate electronic circuit designs in a manner which will maximize the resources of the designed circuit.
Another object of the present invention is to provide a system and method for automatically reducing the pads and ports required for tristate outputs wired together.
Still another object of the present invention is to provide a system and method for adding and manipulating logic at terminals of electronic circuits which maintains the net names at the terminals where such pads and ports are automatically added.